1. Field of the Invention
The present invention relates to a technology of testing a semiconductor integrated circuit.
2. Description of the Related Art
Conventionally, detection of a production defect of an integrated circuit is performed by inputting an appropriate signal value to an input pin of the integrated circuit using a tester such as automatic test equipment (ATE), and by comparing the signal value at the output pin with an expected value. The signal value of the input pin and the expected value of the output pin are collectively called a test pattern. When the integrated circuit includes sequential circuit elements (flip flop (F/F), latch and RAM), the complexity of preparing this test pattern increases remarkably. Therefore, scan design called deterministic stored pattern test (DSPT) is widely employed for the integrated circuit.
FIG. 12 is an explanatory diagram of a DSPT. In the DSPT, test patterns TP (input pattern TPin and output pattern TPout) generated by an automatic test pattern generator (ATPG) are stored into a tester (not shown).
A shift register is formed by sequential circuit elements (mainly F/F) in the integrated circuit 1200. This shift register is called a scan path SP. For convenience, four scan paths SP are formed in FIG. 12. A desired input pattern TPin is shifted in from the input pin 1201 at a test, and the value of the shift register is read from the output pin 1202 to the outside after clock impression. Thus, in the DSPT, setting and reading per test pattern TP are repeated to all the sequential circuit elements structuring the scan paths SP in the integrated circuit 1200.
Recently, along with the increased integration of the integrated circuit, the number of sequential circuit elements included in the inside thereof becomes extremely large. Therefore, the application of the DSPT mentioned above comes to be troublesome in the points of increased test time and test data amount. Therefore, a built-in self-test (BIST) comes to be performed.
FIG. 13 is an explanatory diagram of a BIST. In an integrated circuit 1300, a pseudo random number pattern generator 1301 is arranged at the input side of the scan path SP, and a signature analysis device 1302 is arranged at the output side. When a desired control signal is input to an input pin 1311, the pattern generated by the pseudo random number pattern generator 1301 is output to the scan path SP of the integrated circuit 1300, and the output result from the scan path SP is verified by and stored in the signature analysis device 1302. The signature analysis device 1302 compresses and outputs the output result from the scan path SP to the output pin 1312. In other words, it is verified whether this output is identical to the expected value.
To the pseudo random number pattern generator 1301 and the signature analysis device 1302, a linear feedback shift register (LFSR) is frequently used. Since the signature analysis device 1302 compresses and stores the output result as signature, it is called a multiple input signature register (MISR). In the BIST, the pseudo random number pattern generator 1301 is included in the integrated circuit 1300. Accordingly, it is possible to generate quite a large number of test patterns in a short time, and to greatly reduce the test data amount to load to the tester for compressing the test result by the signature analysis device (MISR) 1302.
The MISR is used for compressing the output data in the BIST. Once a value indicating an unknown state (hereinafter, “unknown value”) is taken in, all the registers in the MISR become unknown state, and test cannot be performed. In general, the sequential circuit elements including RAM in the integrated circuit are in unknown state when power is turned on. The process of automatic test pattern generator (ATPG) is simplified by handling the output of the circuit portion that cannot be tested as unknown value. Therefore, it is necessary to handle unknown state. Furthermore, there are cases when it is necessary to cope with unknown values output according to a large amount of unknown states.
Furthermore, along with the increase of the circuit scale of the integrated circuit, the increase of test time and test data amount comes to be problems. As a test data amount reduction technology in combination of DSPT and BIST to cope with the problems, for example bist aided scan test) (BAST) technology is proposed (for example, Japanese Patent Application Laid-Open No. 2002-236144).
FIG. 14 is an explanatory diagram of the BAST (technology). In the BAST, the integrated circuit 1400 having scan paths SP includes the pseudo random number pattern generator 1301 and the signature analysis device 1302 used in the BIST. The pattern correcting device 1401 corrects the signal of the pseudo random number pattern generator 1301 using the external input. The unknown value mask device 1402 masks the unknown value to be output to the signature analysis device 1302. Thus, the same quality as that of the DSPT is maintained, and the test data and test time are greatly reduced by the DSPT.
However, along with miniaturization of an integrated circuit, new kinds of tests are added to cope with new fault mode, recently. Therefore, it is necessary to further compress test data.
FIG. 15 is an explanatory diagram of a control example of a pattern correcting device in the conventional BAST. In the integrated circuit 1500 in FIG. 15, test pattern is corrected by the input correcting circuit 1501 so that the test pattern generated by PRPG becomes the test pattern generated by ATPG. When the test pattern (PRPG) is corrected by the input correcting circuit 1501, the control signal designating address corresponding to the correction portion of the scan path is input from a tester.
For example, the integrated circuit 1500 has 16 scan paths, and 4-bit signal is required to designate the correction portion of the scan path. Furthermore, 4-bit signal is required for each correction portion, and 8 bits are necessary when there are 2 correction portions. Since the control signal includes information indicating contents of the control besides address information, more number of bits is required. Above control signal is generated as test data in the BAST, the test data amount increases in proportion with the number of correction portions.